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this is information on a product in full production. november 2013 docid025613 rev 1 1/14 a6932h1.2 2 a uldo linear regulator for automotive applications datasheet - production data features ? aec-q100 compliant ? 2 v to 14 v input voltage range ? 200 m ?? r ds(on) max. ? 200 a quiescent current at any load ? excellent load and line regulation ? adjustable from 1.2 v to 5 v ? 1% voltage regulation accuracy ? short-circuit protection ? thermal shutdown ? hsop-8 package applications ? dedicated to automotive applications description the a6932h1.2 ultra low drop output linear regulator operates from 2 v to 14 v and is able to support output current up to 2 a. designed with an internal 50 m ? n-channel mosfet, it can be used for on-board dc-dc conversions saving in real estate, list of components, low noise generation and power dissipation. the a6932h1.2 device is available as adjustable version from 1.2 v to 5 v with a voltage regulation accuracy of 1%. the upper current limit is fixed at 2.5 a to control the current in short-circuit condition within 8%. the current is sensed in the power mos in order to limit the power dissipation. the device is also provided with a thermal shutdown that limits the internal temperature at 150 c with a hysteresis of 20 c. the a6932h1.2 device provides the enable and the power good functions . table 1. device summary hsop-8 figure 1. typical operating circuit /+ 5 5 5 & & 9 rxw 9lq 9 wr 9 (1 9l q 9rxw )% *1' 1& /+ & 9wr 9 3*22' 1& $+ $0 part number package packaging a6932h1.2 hsop-8 tube a6932h1.2tr hsop-8 tape and reel www.st.com
contents a6932h1.2 2/14 docid025613 rev 1 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 demonstration board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.3 component part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3 loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
docid025613 rev 1 3/14 a6932h1.2 pin settings 14 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description (1 9lq )% 3*22' 9rxw *1' 1& 1& (1 9lq )% 3*22' 9rxw *1' 1& 1& $0 table 2. pin description name pin no. description 1 en enables the device when connected to vin and disables it when forced to gnd. 2 vin supply voltage. this pin is connected to the drain of the internal n-mos. connect this pin to a capacitor larger than 10 f. 3fb connecting this pin to a voltage divide r it is possible to program the output voltage between 1.2 v and 5 v. 4vout regulated output voltage. this pin is con nected to the source of the internal n-mos. connect this pin to a capacitor of 10 f. 5 pgood power good output. the pin is open dr ain and detects the output voltage. it is forced low if the output voltage is lower than 90% of the programmed voltage. 6 gnd ground pin 7, 8 nc1 - nc2 internally not connected.
maximum ratings a6932h1.2 4/14 docid025613 rev 1 2 maximum ratings 2.1 absolute maximum ratings 2.2 thermal data 3 block diagram figure 3. internal block diagram table 3. absolute maximum ratings symbol parameter value unit v in vin and pgood 14.5 v en, out and adj -0.3 to (vin +0.3) v table 4. thermal data symbol parameter value unit r thja maximum thermal resistan ce junction ambient 34 (1) 1. package mounted on board. ? c/w t max maximum junction temperature 150 ? c t stg storage temperature range -65 to 150 ? c
docid025613 rev 1 5/14 a6932h1.2 electrical characteristics 14 4 electrical characteristics table 5. electrical characteristics (t a = -40 c to 85 c, v in = 5 v unless otherwise specified) symbol parameter test condition min. typ. max. unit v in operating supply voltage 2 14 v v o output voltage t a = 25 c 1.188 1.2 1.212 v 1.175 1.212 line regulation v in = 2.5 v 10%; i o = 10 ma 5 mv v in = 3.3 v 10%; i o = 10 ma 5 mv v in = 5 v 10%; i o = 10 ma 5 mv load regulation v in = 3.3 v; 0.1 a < i o < 2 a 15 mv r ds(on) drain source on resistance 200 m ? i occ current limiting t a = 25 c 2.3 2.5 2.7 a 2.85 iq quiescent current 0.2 0.4 ma ish shutdown current t a = 25 c 25 a 29 ripple rejection f = 120 hz, i o = 1 a v in = 5 v, ? v in = 2 vpp 60 75 db ven en input threshold 0.5 0.65 0.8 v pgood threshold vo rise 90 %vo pgood hysteresis 10 %vo pgood saturation ipgood = 1 ma 0.2 0.4 v
typical electrical performance a6932h1.2 6/14 docid025613 rev 1 5 typical electrical performance figure 4. output voltage vs. junction temperature figure 5. quiescent current vs. junction temperature figure 6. shutdown current vs. junction temperature
docid025613 rev 1 7/14 a6932h1.2 application information 14 6 application information 6.1 application circuit figure 7. demonstration board application circuit equation 1 6.2 demonstration board layout figure 8. demonstration board layout a6932h1.2 /+ 5 5 5 & & 9 rxw 9lq 9 wr 9 (1 9l q 9rxw )% *1' 1& /+ & 9wr 9 3*22' 1& $+ $0 v out 1.2 r 2 ------- - r 1 r 2 + ?? ? =
application information a6932h1.2 8/14 docid025613 rev 1 6.3 component part list table 6. component part list reference part number description manufacturer c1 grm32er6c226ke20b 22 ? f, 16 v murata c2 grm32er6c226ke20b 22 ? f, 16 v murata r1 n. m. r2 0 ? r3 100 k ?
docid025613 rev 1 9/14 a6932h1.2 component selection 14 7 component selection 7.1 input capacitor the input capacitor value depends on a lot of factors such as load transient requirements, input source (battery or dc/dc converter) and its distance from the input cap. usually a 47 f is enough for any application but a much lower value can be sufficient in many cases. 7.2 output capacitor the output capacitor choice depends basic ally on the load transient requirements. tantalum, special polymer, poscap and aluminum capacitors are good and offer very low esr values. multilayer ceramic ca ps have the lowest esr and can be required for particular applications. nevertheless in several applications they are ok, the loop stability issue has to be considered (see loop stability section). in table 7 is a list of some suggested capacitor manufacturers. 7.3 loop stability the stability of the loop is affect ed by the zero introd uced by the output capacitor. the time constant of the zero is given by: equation 2 table 7. suggested capacitor manufacturer type cap value (f) rated voltage (v) murata ceramic 1 to 47 4 to 16 panasonic ceramic 1 to 47 4 to 16 taiyo yuden ceramic 1 to 47 4 to 16 tdk ceramic 1 to 47 4 to 16 tokin ceramic 1 to 47 4 to 16 sanyo poscap 1 to 47 4 to 16 panasonic sp 1 to 47 4 to 16 kemet tantalum 1 to 47 4 to 16 t esr c out ? =
component selection a6932h1.2 10/14 docid025613 rev 1 equation 3 this zero helps to increase the phase margin of the loop until the time constant is higher than some hundreds of ns, depending also on the output voltage and current. so, using very low esr ceramic capacitors co uld produce oscillations at the output, in particular when regulating high output voltages (adjustable version). to solve this issue is sufficient to add a small capacitor (e.g. 1 nf to 10 nf) in parallel to the high side resistor of the external divider, as shown in figure 9 . figure 9. compensation network the thermal resistance junction to ambient of the demonstration board is approximately 34 c/w. this mean that, considering an ambient te mperature of 60 c and, a maximum junction temperature of 150 c, the maximum power that the device can handle is 2.7 w. this means that the device is able to deliver a dc output current of 2 a only with a very low dropout. f zerp 1 2 ? esr c out ? ? ----------------------------------------------- = l6932h1.2 r1 r2 r3 c1 c2 vout=1.2v to 5v vin=2v to 14v 1 2 3 4 5 6 7 8 en vin vout pgood fb gnd nc2 nc1 c3 l6932h1.2 r1 r2 r3 c1 c2 vout=1.2v to 5v vin=2v to 14v 1 2 3 4 5 6 7 8 en vin vout pgood fb gnd nc2 nc1 c3 a6932h1.2
docid025613 rev 1 11/14 a6932h1.2 package information 14 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 10. hsop-8 package outline +623
package information a6932h1.2 12/14 docid025613 rev 1 table 8. hsop-8 package mechanical data symbol dimensions (mm) note min. typ. max. a 1.43 1.55 1.68 a1 0.03 0.08 0.13 a2 1.40 1.47 1.55 b 0.35 0.41 0.49 c 0.19 0.20 0.25 d 4.80 4.93 4.98 (1) 1. dimension ?d? does not include mold flash, protrusions or gate burrs. d1 according to pad size (2) 2. the size of exposed pad is variable depending of leadf rame design pad size. end user should verify ?d1? and ?e2? dimensions fo r each device application. e 5.84 5.99 6.20 e1 3.81 3.94 3.99 (3) 3. dimension ?e1? does not include interlead flash or pr otrusions. interlead flash or protrusions shall not exceed 0.25 mm per side. e2 according to pad size (2) e 1.27 h 0.25 0.33 0.41 l 0.41 0.64 0.89 k 0 5 8 degrees ccc 0.10
docid025613 rev 1 13/14 a6932h1.2 revision history 14 9 revision history table 9. document revision history date revision changes 29-nov-2013 1 initial release.
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